Veryl Playground
BUILD ▶
FORMAT ▶
Select Example
Hello, World!
Half Adder
Source Code
// module definition module ModuleA #( param ParamA: u32 = 10, const ParamB: u32 = 10, // trailing comma is allowed ) ( i_clk : input clock , i_rst : input reset , i_sel : input logic , i_data: input logic
[2], // `[]` means unpacked array o_data: output logic
, // `<>` means packed array ) { // const parameter declaration // `param` is not allowed in module const ParamC: u32 = 10; // variable declaration var r_data0: logic
; var r_data1: logic
; // value binding let _w_data2: logic
= i_data; // always_ff statement with reset // `always_ff` can take a mandatory clock and a optional reset // `if_reset` means `if (i_rst)`. This conceals reset porality // `()` of `if` is not required // `=` in `always_ff` is non-blocking assignment always_ff (i_clk, i_rst) { if_reset { r_data0 = 0; } else if i_sel { r_data0 = i_data[0]; } else { r_data0 = i_data[1]; } } // always_ff statement without reset always_ff (i_clk) { r_data1 = r_data0; } assign o_data = r_data1; }
Output