Operator Precedence

In expression, operator precedence is almost the same as SystemVerilog.

OperatorAssociativityPrecedence
() [] :: .LeftHighest
+ - ! ~ & ~& | ~| ^ ~^ ^~ (unary)Left
**Left
* / %Left
+ - (binary)Left
<< >> <<< >>>Left
<: <= >: >=Left
== != === !== ==? !=?Left
& (binary)Left
^ ~^ ^~ (binary)Left
| (binary)Left
&&Left
||Left
= += -= *= /= %= &= ^= |=
<<= >>= <<<= >>>=
None
{}NoneLowest