Operator Precedence
In expression, operator precedence is almost the same as SystemVerilog.
| Operator | Associativity | Precedence |
|---|---|---|
() [] :: . | Left | Highest |
+ - ! ~ & ~& | ~| ^ ~^ (unary) | Left | |
** | Left | |
* / % | Left | |
+ - (binary) | Left | |
<< >> <<< >>> | Left | |
<: <= >: >= | Left | |
== != ==? !=? | Left | |
& (binary) | Left | |
^ ~^ (binary) | Left | |
| (binary) | Left | |
&& | Left | |
|| | Left | |
= += -= *= /= %= &= ^= |= <<= >>= <<<= >>>= | None | |
{} inside outside if case switch | None | Lowest |