1. Introduction
  2. Features
  3. Getting Started
    ❱
    1. Installation
    2. Hello, World!
  5. Code Examples
    ❱
    1. Module
    2. Instantiation
    3. Interface
    4. Package
  7. Language Reference
    ❱
    1. Source Code Structure
    2. Lexical Structure
      ❱
      1. Operator
      2. Number
      3. Array Literal
    4. Data Type
      ❱
      1. Builtin Type
      2. User Defined Type
      3. Array
      4. Clock / Reset
    6. Expression
      ❱
      1. Operator Precedence
      2. Function Call
      3. Concatenation
      4. If
      5. Case / Switch
      6. Bit Select
      7. Range
      8. Msb / Lsb
      9. Inside / Outside
      10. Type Cast
    8. Statement
      ❱
      1. Assignment
      2. Function Call
      3. If
      4. Case / Switch
      5. For
      6. Return
      7. Let
    10. Declaration
      ❱
      1. Variable
      2. Parameter
      3. Register
      4. Combinational
      5. Assign
      6. Function
      7. Initial / Final
      8. Attribute
      9. Generate
      10. Instantiation
      11. Named Block
      12. Import / Export
    12. Module
    13. Interface
    14. Package
    15. SystemVerilog Interoperation
    16. Visibility
    17. Foreign Language Integration
    18. Integrated Test
    19. Generics
      ❱
      1. Default Parameter
      2. Prototype
    21. Clock Domain Annotation
      ❱
      1. Unsafe CDC
    23. Standard Library
  9. Development Environment
    ❱
    1. Project Configuration
      ❱
      1. Build
      2. Format
      3. Lint
      4. Test
      5. Publish
    3. Dependencies
    4. Publish Project
    5. Directory Layout
    6. Formatter
    7. Linter
    8. Simulator
    9. Language Server
    10. Compatibility
    11. Documentation
    12. GitHub Action
    13. Source Map
    14. verylup
  11. Appendix
    ❱
    1. Formal Syntax
    2. Semantic Error