1.
Introduction
2.
Features
3.
Getting Started
❱
3.1.
Installation
3.2.
Hello, World!
4.
Code Examples
❱
4.1.
Module
4.2.
Instantiation
4.3.
Interface
4.4.
Package
5.
Language Reference
❱
5.1.
Source Code Structure
5.2.
Lexical Structure
❱
5.2.1.
Operator
5.2.2.
Number
5.2.3.
Array Literal
5.3.
Data Type
❱
5.3.1.
Builtin Type
5.3.2.
User Defined Type
5.3.3.
Array
5.3.4.
Clock / Reset
5.4.
Expression
❱
5.4.1.
Operator Precedence
5.4.2.
Function Call
5.4.3.
Concatenation
5.4.4.
If
5.4.5.
Case
5.4.6.
Bit Select
5.4.7.
Range
5.4.8.
Msb / Lsb
5.4.9.
Inside / Outside
5.5.
Statement
❱
5.5.1.
Assignment
5.5.2.
Function Call
5.5.3.
If
5.5.4.
Case
5.5.5.
For
5.5.6.
Return
5.5.7.
Let
5.6.
Declaration
❱
5.6.1.
Variable
5.6.2.
Parameter
5.6.3.
Register
5.6.4.
Combinational
5.6.5.
Assign
5.6.6.
Function
5.6.7.
Initial / Final
5.6.8.
Attribute
5.6.9.
Generate
5.6.10.
Instantiation
5.6.11.
Named Block
5.6.12.
Import / Export
5.7.
Module
5.8.
Interface
5.9.
Package
5.10.
SystemVerilog Interoperation
5.11.
Visibility
5.12.
Foreign Language Integration
5.13.
Integrated Test
5.14.
Generics
6.
Development Environment
❱
6.1.
Project Configuration
6.2.
Dependencies
6.3.
Publish Project
6.4.
Directory Layout
6.5.
Formatter
6.6.
Linter
6.7.
Simulator
6.8.
Language Server
6.9.
Compatibility
6.10.
Documentation
6.11.
GitHub Action
7.
Appendix
❱
7.1.
Formal Syntax
7.2.
Semantic Error
Light
Rust
Coal
Navy
Ayu
The Veryl Hardware Description Language
English
日本語
Declaration
In this chapter, we’ll discuss about declaration.