Attribute

Attribute can annotate some declarations like variable declaration.

sv Attribute

sv attribute represents SystemVerilog attribute. It will be transpiled to SystemVerilog attribute (* *).

module ModuleA {
    #[sv("ram_style=\"block\"")]
    let _a: logic<10> = 1;
    #[sv("mark_debug=\"true\"")]
    let _b: logic<10> = 1;
}

allow Attribute

allow attribute is used to disable specified lint check.

module ModuleA {
    #[allow(unused_variable)]
    let a: logic<10> = 1;
}

Available lint names are below:

• unused_variable
• missing_reset_statement
• missing_port

ifdef/ifndef Attribute

ifdef and ifndef attribute is used to control whether the annotated code block is enabled by defined value. If DEFINE_A is defined, the code block with #[ifdef(DEFINE_A)] is enabled, and the code block with #[ifndef(DEFINE_A)] is disabled.

module ModuleA {
    #[ifdef(DEFINE_A)]
    {
        let _a: logic<10> = 1;
    }

    #[ifndef(DEFINE_A)]
    {
        let _b: logic<10> = 1;
    }
}