SystemVerilog Interoperation

If you want to access to items of SystemVerilog, $sv namespace can be used. For example, “ModuleA” in SystemVerilog source code can be accessed by $sv::ModuleA. Veryl don’t check the existence of the items.

Veryl compiler emits the path name as is excluding $sv::. Therefore, symbols in other HDLs like Verilog/VHDL can be refered through $sv:: too. It depeneds on implementation (e.g. simulator, synthesizer) whether each symbols can be resolved.

module ModuleA {
    let _a: logic = $sv::PackageA::ParamA;

    inst b: $sv::ModuleB;
    inst c: $sv::InterfaceC;
}

To access some identifiers which are used as Veryl’s keywords, raw identifier can be used.

module ModuleA (
    i_clk: input clock,
) {
    inst a: $sv::ModuleA (
        // clock: i_clk
        // ^ this is syntax error because `clock` is a keyword
        // Instead of it, `r#clock` can be used
        r#clock: i_clk,
    );
}

Macro Reference

Macros defined by `define in SystemVerilog can be referred through $define namespace. A reference under $define is emitted as a macro reference with a backquote prefix. For example, $define::WIDTH is emitted as `WIDTH. As with $sv, the rest of the path is emitted with :: separators, so a macro expanding to a package name can be used to refer its members. Veryl doesn’t check the existence and the value of the macros.

module ModuleA (
    i_a: input logic<$define::WIDTH>,
) {
    const A: u32           = $define::A;
    const B: u32           = $define::PKG::B;
    var   c: $define::TYPE;
    assign c = A + B;
}